Augusto Vega · Ph.D.

IBM T. J. Watson Research Center · Yorktown Heights, NY · ajvega at us dot ibm dot com

I am a Senior Research Staff Member at the IBM T. J. Watson Research Center (NY, USA) involved in R+D work in the areas of heterogeneous systems, embedded designs, and edge AI computing. I made contributions to the field with top-tier publications (e.g. in MICRO and PACT) and have been appointed as General Chair of the 2024 International Symposium on Computer Architecture (ISCA), the flagship conference in computer architecture. I have more than 20 issued US patents and others pending. I also have several peer-reviewed publications and a co-guest edited book on rugged embedded systems. As a Research Staff Member at IBM, I have helped spawn off the new area of cloud-backed, swarm-AI edge cognition systems with application to autonomous/connected vehicles, drones, wearable devices, mobile health monitoring and cyber-physical systems, among others. Today, I am the CTO of the DARPA-funded EPOCHS project (currently ongoing), and I previously contributed to the DARPA PERFECT program. I have also served on multiple conference technical program committees.

Education

Universitat Politècnica de Catalunya (UPC, Spain)

Ph.D. Degree in Computer Architecture (“with highest honor")
Thesis: “Performance and Power Optimizations in Chip Multiprocessors for Throughput-Aware Computation”
Advisors: Prof. Alex Ramírez and Prof. Mateo Valero

Grade: Summa Cum Laude (“with highest honor")

2013

Universitat Politècnica de Catalunya (UPC, Spain)

M.Sc. Degree in Computer Architecture, Networks and Systems
Thesis: “Performance, Power and Thermal Modeling in 3D Die-Stacking Architectures”
Advisors: Prof. Alex Ramírez and Prof. Mateo Valero
2009

University of Buenos Aires (UBA, Argentina)

Computer Engineering Degree
Thesis: “A Framework for the Evaluation of Memory Organizations in Simultaneous Multithreading Environments”
Advisor: Prof. José Luis Hamkalo
2007

Experience

Research Staff Member

IBM T. J. Watson Research Center (NY, USA)

Conduct highly qualified research activities within the Efficient and Resilient Systems group (led by Dr. Pradip Bose). Involved in R+D work in the areas of heterogeneous systems, embedded designs, and edge AI computing. As a Research Staff Member at IBM, I have helped spawn off the new area of cloud-backed, swarm-AI edge cognition systems with application to autonomous/connected vehicles, drones, wearable devices, mobile health monitoring and cyber-physical systems, among others. I am the CTO of the DARPA-funded EPOCHS project (currently ongoing), and I previously contributed to the DARPA PERFECT program.
In the past, I also conducted R+D work in support of IBM System p and Data Centric Systems, with primary focus on power-aware computer architectures and associated system solutions. Issued several invention patents and published several papers in top-tier conferences and journals.

2013 - Present

Staff Engineer

IBM T. J. Watson Research Center (NY, USA)

Developed techniques to reduce chip power consumption in multicore/manycore chips for multi-threaded applications, exploiting core folding, frequency/voltage scaling and low-power (“sleep”) modes. Developed an infrastructure to evaluate these power-reduction techniques in real POWER processors. Worked on applications for Unmanned Aerial Vehicles (UAVs) to adapt them to operate under harsh conditions such as high performance requirements and tight power budgets. Worked and developed the processor-in-regfile (PIR) technique which consists of computation logic embedded in a register file to accelerate parallel programs.

2010 - 2013

Junior Researcher

Barcelona Supercomputing Center (Spain)

Devised a last-level cache (LLC) organization to improve bandwidth in multicore/manycore chips. In contrast to state-of-the-art LLC designs, this organization avoids data replication and, hence, does not require keeping data coherent. This results in better hit rates and higher bandwidth compared to a conventional (data coherent) LLC. Developed TaskSim, a modular CMP-architecture performance modeling tool.

2007 - 2010

Research Assistant

University of Buenos Aires (Argentina)

Devised a first-level cache (L1) optimized for SMT-enabled chip multiprocessors. Developed a performance model to study first-level caches in SMT-enabled chip multiprocessors.

2002 - 2007

Teaching Assistant

University of Buenos Aires (Argentina)

Introductory and advanced undergraduate courses on computer architectures and programming.

2002 - 2007

Other Professional Activities

  • Senior Member of the Institute of Electrical and Electronics Engineers (IEEE).
  • General Chair, 2024 International Symposium on Computer Architecture (ISCA), to be announced.
  • "Computer Systems Design" Professional Interest Community Chair, IBM T. J. Watson Research Center, 2017—2021.
  • Program Committee Member, 2021 Design Automation Conference (DAC), San Francisco (USA), December 2021.
  • Ph.D. Dissertation Committee Member (two committees: 2020 and 2017).
  • Program Committee Member, 2020 International Conference on Parallel Processing (ICPP), virtual event, August 2020.
  • Program Committee Member, 2020 Design Automation Conference (DAC), virtual event, July 2020.
  • Industrial Chair, 2018 ACM International Conference on Computing Frontiers (CF), Italy, May 2018.
  • Finance Chair, 2017 IEEE/ACM International Symposium on Microarchitecture (MICRO), Boston (USA), October 2017.
  • Program Chair, SRC Executive Technical Advisory Board Summer Study, Dallas (USA), June 2017.
  • External Program Committee Member, 2017 IEEE/ACM International Symposium on Computer Architecture (ISCA), Toronto (Canada), June 2017.
  • Program Committee Member, 2017 ACM International Conference on Computing Frontiers (CF), Siena (Italy), May 2017.
  • Program Committee Member, 2016 ACM International Conference on Computing Frontiers (CF), Como (Italy), May 2016.
  • Book on Rugged Embedded Systems: Computing in Harsh Environments, Morgan Kaufmann Publishers, December 2016.
    Book website
  • Guest Editor, IEEE Micro Special Series on Harsh Chips, IEEE Micro Journal, 2014.
  • Guest Editor, IEEE JETCAS Special Issue on Robust and Energy-Secure Systems, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, June 2014.
  • Technology Transfer Facilitator, SRC Global Research Collaboration (GRC) Industry Liaison Program.
  • Organizer of multiple tutorials and workshops, including CogArch, SARA, HARSH, and ESSA.

Publications & Conference Presentations

Conference Papers

  • A. Vega, J.-D. Wellman, H. Franke, A. Buyuktosunoglu, P. Bose, A. Amarnath, H. Kassa, S. Pal, R. Dreslinski. STOMP: Agile Evaluation of Scheduling Policies in Heterogeneous Multi-Processors. In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech 2021). Virtual event. March 2021.
  • P. Bose, A. Vega, S. Adve, V. Adve, S. Misailovic, L. Carloni, K. Shepard, D. Brooks, V. Janapa Reddi, G.-Y. Wei. Secure and Resilient SoCs for Autonomous Vehicles. In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech 2021). Virtual event. March 2021.
  • E. Sisbot, A. Vega, A. Paidimarri, J.-D. Wellman, A. Buyuktosunoglu, P. Bose, D. Trilla. Multi-Vehicle Map Fusion using GNU Radio. In Proceedings of the GNU Radio Conference (GRCon 2019). Huntsville (AL). September 2019.
  • A. Vega, P. Bose. Cognitive IoT Systems via Adaptive Swarm Intelligence. In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech 2019). Albuquerque (NM). March 2019.
  • A. Vega, A. Buyuktosunoglu, P. Bose. Towards “Smarter” Vehicles through Cloud-Backed Swarm Cognition. In Proceedings of the IEEE Intelligent Vehicles Symposium (IV 2018). Changshu (China). June 2018.
  • A. Vega, A. Buyuktosunoglu, P. Bose. Enabling a Low-Power IoT through Swarming Operation. In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech 2018). Miami (USA). March 2018.
  • R. Bertran, P. Bose, D. Brooks, J. Burns, A. Buyuktosunoglu, N. Chandramoorthy, E. Cheng, M. Cochet, S. Eldridge, D. Friedman, H. Jacobson, R. Joshi, S. Mitra, R. Montoye, A. Paidimarri, P. Parida, K. Skadron, M. Stan, K. Swaminathan, A. Vega, S. Venkataramani, C. Vezyrtzis, G.-Y. Wei, J.-D. Wellman, M. Ziegler. Very Low Voltage (VLV) Design. In Proceedings of the IEEE International Conference on Computer Design (ICCD 2017). Boston (USA). November 2017.
  • A. Vega, A. Buyuktosunoglu, P. Bose. Secure Swarm Intelligence: A New Approach to Many-Core Power Management. In Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2017). Taipei (Taiwan). July 2017.
  • P. Parida, A. Sridhar, A. Vega, M. Schultz, M. Gaynes, O. Ozsun, G. McVicker, T. Brunschwiler, A. Buyuktosunoglu, T. Chainer. Thermal Model for Embedded Two-Phase Liquid Cooled Microprocessor. In Proceedings of the IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm 2017). Orlando (USA). June 2017. Honorable Mention Paper Award.
  • A. Vega, S. Eldridge, A. Buyuktosunoglu, P. Bose. Mobile Cognition: Enabling Deep Learning Computing in the Internet of Things Era. In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech 2017). Reno (USA). March 2017.
  • C. Tyberg, A. Vega, et al. Co-Design for 3D Silicon Integration with Embedded Two Phase Cooling. In Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech 2016). Orlando (USA). March 2016.
  • P. Parida, A. Vega, A. Buyuktosunoglu, P. Bose, T. Chainer. Embedded Two-Phase Liquid Cooling for Increasing Computational Efficiency. In Proceedings of the IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm 2016). Las Vegas (USA). May-June 2016.
  • A. Vega, C.-C. Lin, K. Swaminathan, A. Buyuktosunoglu, S. Pankanti, P. Bose. Resilient, UAV-Embedded Real-Time Computing. In Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD 2015). New York City (USA). October 2015.
  • L. Wang, A. Vega, A. Buyuktosunoglu, P. Bose, K. Skadron. Power-Efficient Embedded Processing with Resilience and Real-Time Constraints. In Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2015). Rome (Italy). July 2015.
  • L. Wang, J. Rivers, M. Gupta, A. Vega, A. Buyuktosunoglu, P. Bose, K. Skadron. Resilience and Real-Time Constrained Energy Optimization in Embedded Processor Systems. In Proceedings of the 10th Workshop on Silicon Errors in Logic-System Effects (SELSE 2014). Stanford, California (USA). April 2014.
  • A. Vega, A. Buyuktosunoglu, H. Hanson, P. Bose, S. Ramani. Crank It Up or Dial It Down: Coordinated Multiprocessor Frequency and Folding Control. In Proceedings of the 46th International Symposium on Microarchitecture (MICRO 2013). Davis, California (USA). December 2013.
  • A. Vega, A. Buyuktosunoglu, P. Bose. SMT-Centric Power-Aware Thread Placement in Chip Multiprocessors. In Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT 2013). Edinburgh (Scotland). September 2013. Nominated for Best Paper.
  • D. Sreedhar, J. Derby, A. Vega, B. Rogers, C. Johnson, R. Montoye. Processor Architecture for Software Implementation of Multi-sector G-Rake Receivers for HSUPA Wireless Infrastructure. In Proceedings of the 38th International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013). Vancouver (Canada). May 2013.
  • P. Bose, A. Buyuktosunoglu, J. Darringer, M. Gupta, M. Healy, H. Jacobson, I. Nair, J. Rivers, J. Shin, A. Vega, A. Weger. Power Management of Multi-Core Chips: Challenges and Pitfalls. In Proceedings of the 2012 Conference on Design, Automation and Test in Europe (DATE 2012). Dresden (Germany). March 2012.
  • A. Vega, P. Bose, A. Buyuktosunoglu, J. Derby, M. Franceschini, C. Johnson, R. Montoye. Architectural Perspectives of Future Wireless Base Stations based on the IBM PowerEN Processor. In Proceedings of the 18th International Symposium on High-Performance Computer Architecture (HPCA 2012). New Orleans (USA). February 2012.
  • A. Rico, F. Cabarcas, C. Villavieja, M. Pavlovic, A. Vega, Y. Etsion, A. Ramírez, M. Valero. On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels. In Proceedings of the 7th International Conference on High- Performance and Embedded Architectures and Compilers (HIPEAC 2012). Paris (France). January 2012.
  • J. Derby, T. Heil, M. Franceschini, A. Krishna, R. Montoye, D. Sreedhar, A. Vega, H. Yeo, C. Johnson. Vector-Based Acceleration in the IBM PowerEN Processor To Enable Software-Defined Radio. In Proceedings of the 2011 Software Defined Radio Technical Forum (SDR 2011). Washington DC (USA). November 2011.
  • A. Vega, F. Cabarcas, A. Ramírez, M. Valero. Breaking the Bandwidth Wall in Chip Multiprocessors. In Proceedings of the 11th International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS 2011). Samos (Greece). July 2011.

Journals

  • A. Vega, A. Buyuktosunoglu, D. Callegaro, M. Levorato, P. Bose. Cloud-Backed Mobile Cognition: Power-Efficient Deep Learning in the Autonomous Vehicle Era. Springer Computing. To be published.
  • H. Sasaki, A. Buyuktosunoglu, A. Vega, P. Bose. Mitigating Power Contention: A Scheduling Based Approach. IEEE Computer Architecture Letters. May 2017.
  • A. Vega, S. Mitra, S. Sethumadhavan. Guest Editorial: Robust and Energy-Secure Systems. In IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS). June 2014.
  • P. Tembey, A. Vega, A. Buyuktosunoglu, D. Da Silva, P. Bose. SMT switch: Software Mechanisms for Power Shifting. In IEEE Computer Architecture Letters. July-December 2013.
  • V. Desmet, S. Girbal, A. Ramírez, O. Temam, A. Vega. ArchExplorer for Automatic Design Space Exploration. In IEEE Micro Special Issue: European Multicore Processing Projects. September/October 2010.

Workshop Papers

  • A. Vega, J.-D. Wellman, H. Franke, A. Buyuktosunoglu, P. Bose, A. Amarnath, H. Kassa, S. Pal, R. Dreslinski. STOMP: Agile Evaluation of Scheduling Policies in Heterogeneous Multi-Processors. In Proceedings of the 3rd International Workshop on Domain Specific System Architecture (DOSSA-3). Virtual event. February 2021.
  • A. Vega, P. Bose, A. Buyuktosunoglu. Power Management for CMP/SMT Processors: Some Decision Control Pitfalls. In Proceedings of the 3rd Tutorial/Workshop on Energy-Secure System Architectures (ESSA 2013). Tel Aviv (Israel). June 2013.
  • A. Vega, P. Bose, A. Buyuktosunoglu. Power-Aware Thread Placement in SMT/CMP Architectures. In Proceedings of the 4th Workshop on Energy Efficient Design (WEED 2012). Portland (USA). June 2012.
  • A. Vega, A. Rico, F. Cabarcas, A. Ramírez, M. Valero. Comparing Last-level Cache Designs for CMP Architectures. In Proceedings of the 2nd International Forum on Next-Generation Multicore/Manycore Technologies (IFMT 2010). Saint-Malo (France). June 2010.

Technical Reports and Other Publications

  • A. Vega, A. Amarnath, J.-D. Wellman, H. Kassa, S. Pal, H. Franke, A. Buyuktosunoglu, R. Dreslinski, P. Bose. STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors. arXiv preprint arXiv:2007.14371. 2020.
  • A. Vega. Performance and Power Optimizations in Chip Multiprocessors for Throughput-Aware Computation. Ph.D. Thesis. Department of Computer Architecture, Universitat Politècnica de Catalunya. Barcelona (Spain). July 2013.
  • A. Rico, F. Cabarcas, A. Quesada, M. Pavlovic, A. Vega, C. Villavieja, Y. Etsion, A. Ramírez. Scalable Simulation of Decoupled Accelerator Architectures. In Technical Report UPC-DAC-RR-2010-14. Universitat Politècnica de Catalunya. June 2010.
  • A. Vega. Performance, Power and Thermal Modeling in 3D Die-Stacking Architectures. M.Sc. Thesis. Department of Computer Architecture, Universitat Politècnica de Catalunya. Barcelona (Spain). January 2009.

Posters

  • A. Vega, A. Buyuktosunoglu, H. Hanson, P. Bose, S. Ramani. Crank It Up or Dial It Down: Coordinated Multiprocessor Frequency and Folding Control. In the 46th International Symposium on Microarchitecture (MICRO 2013). Davis, California (USA). December 2013.
  • A. Vega, A. Ramírez, M. Valero. 3D Die-Stacking Architectures: State of the Art. In Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2008). L'Aquila (Italy), July 2008.

Invited Talks

Book on Rugged Embedded Systems